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The simulator for the Intel 80286, Sim286, can be partitioned into two class frameworks where the first framework is an extension of the framework for Sim8088 and the second framework incorporates an event list to simulate the parallel execution of events. We adopt the naming convention used in reference [4] to refer to these two frameworks as the Architecture Framework, captured in Figure 2.4, and the Simulation Framework. The extensions to Sim286 that we report in this paper focus on the Architecture Framework. The interested reader may consult reference [4] for a description of the simulation framework.
The CPU class for Sim286 is extended to include a global descriptor table register, a local descriptor table register, an interrupt descriptor table register and segment registers. The CPU class is shown on the left side of Figure 2.4 with classes DescriptorTableReg, DescriptorTable, and SegRegister drawn beneath CPU. These classes, together with class Register, are the components of our representation of the Intel processor; thus, they form an aggregation relationship with class CPU as illustrated by the diamond connector in the figure. The figure shows that class Register is templated, a feature that facilitated the extension of Sim286 from 16-bit processing to 32-bit processing.
The Sim286 simulator extended Sim8088 to include both real mode and protected mode. This extension is illustrated in Figure 2.4 with classes RealModeBIU and VirtualModBIU derived from the BIU class; the arrow connector in the figure represents the inheritance relationship[6]. The figure also illustrates that the BIU is related to class PrefetchQueue through aggregation. An important feature of Sim286 is the ability to simulate the prefetch and decode of instructions in parallel with other CPU operations.